FPGA training module

This training module aims to introduce the students to the concept of FPGAs, programming them using a higher level language (C++) and synthesizing firmware. We use Xilinx platform. The duration of this training is 1 semester (14 weeks). The detailed syllabus and series of lectures can be found below.

• Course syllabus
• Series of lectures :
  • Lecture 1 Introduction to FPGA and its architecture
  • Lecture 2 FPGA: Parallelism in program execution
  • Lecture 3 FPGA: Clock Frequency, Latency, Pipelining
  • Lecture 4 Introduction to Vivado HLS, Setup
  • Lecture 5 Hands-on with vivado_hls, output review
  • Lecture 6 Hands-on with vivado_hls, Introduction to Pragmas
  • Lecture 7 Vivado HLS: Pragmas & more examples
  • Lecture 8 Vivado HLS: Pragma’s effect on performance
  • Lecture 9 Vivado HLS: More pragmas and Do’s & Don’ts
  • Lecture 10 Vivado HLS: More pragmas and HLS coding styles
  • Lecture 11 LHC, CMS Level-1 Trigger, Project
  • Lecture 12 Project: Re-designing RCT
  • Lecture 13 Introduction to VHDL
  • Lecture 14 Introduction to VHDL contd.