INSTITUTION NAME: University of Wisconsin–Madison

COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : FPGA training module 

CREDITS: 3 credits equivalent

COURSE DESCRIPTION:

Introduction to FPGA programming. Overview of FPGA, design flow, introduction High-Level synthesis and its applications

REQUISITES:

• Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.
• Students need to set-up a Wisconsin computing account and have login access to cmstrigger02 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.

MEETING TIME AND LOCATION:

Zoom coordinates: 

https://cern.zoom.us/j/64311841956?pwd=S7FybCBrWQUNV6qbGZ2rSDyEfA9aad.1

Meeting ID: 643 1184 1956

FPGA Module

Lectures: Tuesdays and Thursday: 11:00 – 12:00 (CT), 12:00 – 13:00 (EST), 18:00 – 19:00 PM (CERN) via zoom

INSTRUCTIONAL MODALITY:

Virtual via zoom. There will be a combination of lectures and hands-on training.

OFFICE HOURS:

• Office hours by appointment. 
• Slack channel to post questions and communicate with instructors :
• https://uwmadisoncms.slack.com/archives/C08BBUTJ33J

INSTRUCTOR CONTACT INFO:

Dr. Varun Sharma

varun.sharma@cern.ch

COURSE LEARNING OUTCOMES:

Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Understand the role and capabilities of FPGAs and High Level Synthesis, and learn to write algorithms for hardware.

COURSE OVERVIEW:

REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:

• No required textbook
• All softwares will be installed in the available machines

HLS manual for reference:        https://docs.amd.com/v/u/en-US/dh0090-vitis-hls-hub

HOMEWORK AND OTHER ASSIGNMENTS:

Week 1-12: Weekly assignments 

Week 13-14: Project

GRADING:

COURSE SCHEDULE/CALENDAR

Deadlines:

• Two weeks from the assignment date 

TOPICS COVERED

Week 1

• Introduction to FPGA and its architecture
• Domain Specifica Accelerators

Week 2

• LHC, CMS Level-1 Trigger, & FPGAs in HEP
• FPGA Architecture & its sub-components

Week 3

• FPGA Processing: Scheduling, Pipeling & DataFlow
• Some concepts of hardware design: Clock Frequency, Latency & Pipelining
• Introduction to Digital Gates

Week 4

• Introduction to Hardware Description Languages: Verilog

Week 5

• Introduction to High Level Synthesis (HLS) & its setup
• First project using Vitis/Vivado HLS

Week 6

• Review project outputs

Data types, Arbitrary Precisions, & Introduction to HLS Pragmas

Week 7

• Understanding HLS Pragma Interface with examples

Week 8

• Understanding HLS Pragma Array_partition with examples
• HLS Pragmas: Array_reshape and Pipeling

Week 9

• HLS Pragmas: Dataflow, Allocation, and Latency
• HLS Pragmas: Stable, Inline, Unroll

Week 10

• Hands-on with Pragmas: Loop unrolling & Optimizations

Week 11

• Overview of Machine Learning
• Autoencoder, Data precision, model quantization, knowledge distillation

Week 12

• Introduction to hls4ml and its tutorial (If time permits)

Week 13-14

• Project