FPGA training module

This training module aims to introduce the students to the concept of FPGAs, programming them using a higher level language (C++) and synthesizing firmware. We use AMD/Xilinx platform. The duration of this training is 1 semester - 12 weeks (2 lectures per week). The detailed syllabus and series of lectures can be found below.

• Course syllabus
• Series of lectures :
  • Lecture 1 Introduction to FPGA and its architecture
  • Lecture 2 Domain Specific Accelerators
  • Lecture 3 LHC, CMS Level-1 Trigger, & FPGAs in HEP
  • Lecture 4 FPGA Architecture & its sub-components
  • Lecture 5 FPGA Processing: Scheduling, Pipelining & DataFlow
  • Lecture 6 Basic concepts of Hardware design & Introduction to digital gates
  • Lecture 7 Introduction to hardware description languages: Verilog
  • Lecture 8 More on Verilog
  • Lecture 9 Introduction to HLS & its setup
  • Lecture 10 First HLS program: steps to create an IP
  • Lecture 11 Review of synthesis output
  • Lecture 12 Data-types (arbitrary precision) & introduction to pragmas
  • Lecture 13 HLS Pragma: Interface
  • Lecture 14 HLS Pragma: Array_partition
  • Lecture 15 HLS Pragma: Array_reshape, Pipeline
  • Lecture 16 HLS Pragma: Dataflow, Allocation, Latency
  • Lecture 17 HLS Pragma: Stable, Inline, Unroll
  • more to be added soon…