INSTITUTION NAME: University of Wisconsin–Madison

COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : GPU & FPGA training module 

CREDITS: 3 credits equivalent

COURSE DESCRIPTION:

Introduction to GPU and FPGA programming. Re-cap on the basics of C++, introduction to the CUDA programming model. Overview of FPGA, design flow, introduction High-Level synthesis and its applications

REQUISITES:

  • Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.
  • Students need to set-up a Wisconsin computing account and have login access to one of the UW GPU nodes and cmstrigger01 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.

MEETING TIME AND LOCATION:

Zoom coordinates: 

https://cern.zoom.us/j/69712006717?pwd=c0pqUGZxbUlFNkVRSWxHc24yL21tdz09

Meeting ID: 697 1200 6717

GPU Module

Lectures: 

Tuesdays 9:00 – 10:00 AM (CT), 10:00 – 11:00 AM (EST), 16:00 – 17:00 (CERN) 

Wednesdays 11:00 – 12:00 PM (CT), 12:00 – 13:00 (EST), 18:00 – 19:00 (CERN) 

via zoom

Note: Subject to change in weeks 5-7 since some lectures will be given by guest lecturers who are experts in the field and may have time conflicts  

FPGA Module

Lectures: Tuesdays and Wednesday: 9:00 – 10:00 AM (CT), 10:00 – 11:00 AM (EST), 16:00 – 17:00 PM (CERN) via zoom

INSTRUCTIONAL MODALITY:

Virtual via zoom. There will be a combination of lectures and hands-on training.

OFFICE HOURS:

INSTRUCTOR CONTACT INFO:

GPU module

Dr. Charis Kleio Koraka

charis.kleio.koraka@cern.ch

FPGA module

Dr. Varun Sharma

varun.sharma@cern.ch

COURSE LEARNING OUTCOMES:

Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Become familiar with the CUDA programming model. Learn how to use and interpret the output of profiling tools. The second part or module will give an introduction to FPGAs and HLS and how to write algorithms for hardware.

COURSE OVERVIEW:

REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:

  • No required textbook
  • All softwares will be installed in the available machines

HLS manual for reference:        https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf

HOMEWORK AND OTHER ASSIGNMENTS:

GPU Module

Weekly assignments for the following weeks

Week 2 : C++ assignment

Week 3 : CUDA assignment

Week 4 : CUDA assignment

Weeks 5-7 : Project

FPGA Module

Week 2-4: Weekly assignments 

Week 5-7: Project

GRADING:

  GPU module FPGA module
Weekly assignments  30% 20%
Final project 20% 30%
Overall  50 % 50 %

COURSE SCHEDULE/CALENDAR

Deadlines:

GPU Module

  • Each weekly assignment is due Friday of the next week (i.e. Week 2 assignment is due end of Week 3 on February the 10th)
  • Final project is due end (by Sunday) of week 7, Friday March 10th.

FPGA Module

  • Each weekly assignment is due Friday of the next week 
  • Final project is due end (by Sunday) of week 7, Friday April 30th.

TOPICS COVERED

GPU Module

Week 1

  • Introduction to the training module 
  • Description of the CPU 
  • Hardware accelerators : types and applications
  • Description of the GPU 
  • GPU vs CPU / GPUs vs FPGAs
  • Heterogeneous computing
  • Computing challenge in HEP
  • GPU applications in HEP

Week 2

  • Introduction to C++ 
    • Core syntax and types
    • Operators
    • Arrays, Pointers & References
    • Control instructions (if/switch,for/while loops etc.)
    • Compound data types (structs, enums etc.)
    • Functions
    • Scopes / namespaces
    • Object Orientation (objects and classes/ constructors & destructors/ inheritance )

Week 3

  • Introduction to CUDA
    • Shell commands to use with GPUs
    • Concept of parallelization
    • GPU jargon
    • CUDA core syntax
    • GPU memory hierarchy and basic memory management
    • Error handling

Week 4

  • Continue the introduction to CUDA
    • CUDA execution model
    • How threads / warp size map to GPU architecture
    • Synchronization at grid and block level
    • Memory access patterns and coalesced memory accesses
    • Static and dynamic shared memory / optimizing memory performance using tiling
    • Race conditions and atomic operations

Week 5 - Week 6 - Week 7

  • Work on assigned project
  • Follow some advanced topics → to be determined. Some examples are :
    • Profiling C++ and CUDA code 
    • Read and interpret profiler output
    • Portability libraries
    • Concurrency using non-default CUDA streams 

FPGA Module

Week 1

  • FPGA – Introduction, why do we need them? different options available in market;
  • Overview of FPGA architecture, programming model and FPGA parallelism vs processor architectures

Week 2

  • Digital systems: some important components used on the FPGAs like registers (flip-flops), DSPs, LUTs;
  • Basic concepts of Hardware design: Clock Frequency, Latency and Pipelining, Throughput

Week 3-4

  • Vivado High-level Synthesis (HLS): Basic overview, understanding of HLS, its purpose, benefit and usage;
  • Mathematical Operations, Conditional statements, Loops, functions in HLS
  • HLS: Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, datatypes for efficient hardware, Design analysis and optimisation and RTL verification;
  • Case study of trigger algorithms developed for the LHC experiments
  • Introduction to CMS experiment and Level-1 Trigger system
  • Basic introduction to VHDL and design flow
  • Quick introduction and guide to HLS4ML

Week 5-6-7

  • Project: Write an algorithm in C/C++; use HLS to make a bit file which can be burned in hardware.

Additional Read (if time permit) :

-   Computation-centric Algorithms

-   Control centric algorithms

-   Integration of multiple programs