INSTITUTION NAME: University of Wisconsin–Madison

COURSE SUBJECT, NUMBER AND TITLE: TAC-HEP : FPGA training module 

CREDITS: 3 credits equivalent

COURSE DESCRIPTION:

Introduction to FPGA programming. Overview of FPGA, design flow, introduction High-Level synthesis and its applications

REQUISITES:

• Familiarity navigating through UNIX based OS. Familiarity with CLI. Elementary knowledge of C or C++.
• Students need to set-up a Wisconsin computing account and have login access to cmstrigger01 machine with Xilinx Vivado tools. Students will be provided instructions for doing so prior to the start of the training.

MEETING TIME AND LOCATION:

Zoom coordinates: 

https://cern.zoom.us/j/69712006717?pwd=c0pqUGZxbUlFNkVRSWxHc24yL21tdz09

Meeting ID: 697 1200 6717

FPGA Module

Lectures: Tuesdays and Wednesday: 9:00 – 10:00 AM (CT), 10:00 – 11:00 AM (EST), 16:00 – 17:00 PM (CERN) via zoom

INSTRUCTIONAL MODALITY:

Virtual via zoom. There will be a combination of lectures and hands-on training.

OFFICE HOURS:

• Office hours by appointment. 
• Slack channel to post questions and communicate with instructors :
• https://uwmadisoncms.slack.com/archives/C04JCTY6SAH

INSTRUCTOR CONTACT INFO:

Dr. Varun Sharma

varun.sharma@cern.ch

COURSE LEARNING OUTCOMES:

Develop an understanding of the differences between different hardware (CPUs / GPUs / FPGAs). Get familiar with their use cases in HEP and develop the ability to identify the ideal hardware accelerator for different HEP applications. Understand the role and capabilities of FPGAs and High Level Synthesis, and learn to write algorithms for hardware.

COURSE OVERVIEW:

REQUIRED TEXTBOOK, SOFTWARE AND OTHER COURSE MATERIALS:

• No required textbook
• All softwares will be installed in the available machines

HLS manual for reference:        https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf

HOMEWORK AND OTHER ASSIGNMENTS:

Week 1-7: Weekly assignments 

Week 8-14: Project

GRADING:

COURSE SCHEDULE/CALENDAR

Deadlines:

• Each weekly assignment is due Friday of the next week 
• Final project is due end (by Sunday) of week 14, Friday April 30th.

TOPICS COVERED

Week 1

• FPGA – Introduction, why do we need them? different options available in market;
• Overview of FPGA architecture, programming model and FPGA parallelism vs processor architectures

Week 2

• Digital systems: some important components used on the FPGAs like registers (flip-flops), DSPs, LUTs;
• Basic concepts of Hardware design: Clock Frequency, Latency and Pipelining, Throughput

Week 3-4

• Vivado High-level Synthesis (HLS): Basic overview, understanding of HLS, its purpose, benefit and usage;
• Mathematical Operations, Conditional statements, Loops, functions in HLS
• HLS: Linear Algebra library functions, DSP library functions, C++ arbitrary precision types, datatypes for efficient hardware, Design analysis and optimisation and RTL verification;
• Case study of trigger algorithms developed for the LHC experiments
• Introduction to CMS experiment and Level-1 Trigger system
• Basic introduction to VHDL and design flow
• Quick introduction and guide to HLS4ML

Week 5-6-7

• Project: Write an algorithm in C/C++; use HLS to make a bit file which can be burned in hardware.

Additional Read (if time permit) :

-   Computation-centric Algorithms

-   Control centric algorithms

-   Integration of multiple programs